1. Field of the Invention
The invention relates to the phase-locked loop (PLL) technology particularly with respect to use in synchronous communication systems.
2. Description of the Prior Art
Phase-locked loops are ubiquitous in modern technologies for locking the loop output frequency to an input reference frequency. Phase-locked loops are widely used in digital communication networks employing synchronous communication for, inter alia, locking to a noisy input reference clock and outputting a clean clock corresponding thereto. In a synchronous network, data is transmitted from one network node to another along with a transmission clock to which it is synchronized. Generally, each node of the network includes a phase-locked loop that locks to a reference clock to generate a local node clock that is utilized for internal timing as well as for transmission with data to other nodes. Data received by a node is entered into an input buffer by the clock transmitted with the data. The data is strobed from the buffer for storage and use at the node by the local node clock generated by the node phase-locked loop. If the local node clock differs in frequency with respect to the clock received with the data, underflow or overflow errors will occur resulting in a loss of data. Overflow errors occur when the data is clocked into the buffer faster than it can be removed. Underflow errors occur when the data is removed from the buffer faster than it is clocked in. Thus, it is appreciated that it is of paramount importance that the clocks utilized in the system be frequency locked with respect to each other.
Another source of error that may result in data loss is phase jitter. Phase jitter is short term phase distortion (noise) experienced by a signal. When a clock plus data is transmitted from one node to another, the signals are contaminated by random phase delays resulting in phase jitter. It is appreciated, however, that the data and clock transmitted therewith remain phase synchronized with respect to each other so that the receiving node can utilize the clock to synchronously input the data. The transmitted clock and the transmitted data experience the same amount of jitter. The received clock and the internal node clock may, however, jitter with respect to each other so that data loss may result.
In networks utilizing synchronous communication, a source clock is designated and the phase-locked loop of a node denoted as a master node locks to the source clock. The PLL clock from the master node is transmitted to a further node to provide a reference clock thereto to which the PLL of the further node locks. The phase-locked loop of the further node then transmits a clock to a still further node. In this manner, in accordance with a protocol established for the network, all of the nodes are frequency locked to the source clock. If the source clock (or master node) should become inoperative, the system switches to a new source clock generally at a location different from the original source clock and generally designates a new master node. Since the source clocks available to a network may vary in frequency within a predetermined tolerance, the entire network must frequency lock to the new source. Such lock-up procedure may require an inordinately large amount of time during which substantial overflow and underflow errors may occur. Networks often utilize error detecting codes for detecting such overflow or underflow errors. The system is then controlled so that messages are repeatedly retransmitted until an error free transmission occurs. This process places an undesirable overhead on the network.
Wide bandwidth phase-locked loops may be utilized that exhibit fast lock-up time but introduce significant phase jitter during the locking process. During frequency lock-up, the phase-locked loop clocks are slipping with respect to each other to an extent that the network is effectively shut down until system wide synchronization has been reestablished. Although the nodes endeavor to transmit messages to each other during lock-up, errors are so prevalent that retransmissions continue until lock-up when the message is received without error.
In such prior art systems utilizing wide bandwidth phase-locked loops, the loop bandwidth is often significantly greater than the maximum bandwidth of the input reference clock to be tracked so as to minimize lock-up time when switching clock sources. Since larger bandwidth results in less phase jitter attenuation, such networks tend to introduced large errors during the lock-up process.
If narrow bandwidth phase-locked loops are utilized in the network, very long lock-up times are experienced. When utilizing narrow bandwidth phase-locked loops, the frequency tolerance of the source clocks must be held to a very narrow limit in order that underflow and overflow errors are held to an acceptably low level during the long lock-up time.
Prior art communication networks also utilize phase-locked loops that gradually converge to a narrow bandwidth mode from a wide bandwidth mode. Such slow convergence processes result in insufficient jitter attenuation during the locking process resulting in significant data transmission errors due to clock slippage.
Thus it is appreciated that in a synchronous communication environment, it is desirable to lock to a new reference clock as fast as possible. During the lock-up time, clock discrepancies such as frequency offset usually result in non-recoverable errors. The present day increase in the complexity of communication networks exacerbate the number of errors arising from a slow locking time. The locking time is the time duration from the introduction of a new clock source to when the node output clocks satisfy the jitter attenuation requirements of the system. Thus, conventional phase-locked loops with relatively long lock-up time result in large frequency offsets and concomitant transmission errors. Increasing the loop bandwidth to reduce the lock-up time results in an undesirably large increase in output jitter. In the conventional phase-locked loop technology, the amount of jitter attenuation decreases exponentially with respect to the duration of the lock-up time.
Thus, it is appreciated from the foregoing that the performance of the phase-locked loop is uniquely the most critical factor in the performance of synchronous communication systems. In present day communication systems, phase-locked loop designs are utilized that have been optimized for systems other than communication systems, such as control systems, which designs are not optimum for communication systems.